Chapter 2

Floorplanning, Macros & Die

Floorplan Starting Requirements

You need the netlist (.v), timing libraries (.lib), physical libraries (.lef) and constraints (.sdc).

Floorplanning is the first major implementation step and largely sets chip quality. Here you fix the chip/block size, allocate power-routing resources, place the hard macros and reserve area for standard cells.

KEY Floorplan inputs: .v, .lib, .lef, .sdc - it decides die size, macro placement and power resources.

Macro Placement Guidelines

Keep macros near the chip periphery unless there is a strong reason to place them in the core; core macros force long detour routing and make power delivery harder, raising IR-drop risk.

Place each macro close to the fixed elements it connects to (IOs, preplaced macros); use flight lines in the GUI to verify connectivity.

Orient macros so pin-to-pin distance is minimised.

Leave enough room around macros for signal routing and the power grid; use a trial-route congestion map to spot hotspots and adjust.

Remove dead space so more area is available for logic; changing the aspect ratio can help close open fields.

Reserve adequate space for the power grid based on estimated power consumption, or routing problems will appear later.

KEY Macros to the periphery, near their connections, well oriented, with room reserved for routing and power.

Wrong-Side Pin Assignment

At the top level the chip is split into blocks, and IO pins are placed according to how neighbouring blocks communicate. Forcing pins onto the left and right when they should be top and bottom creates routing congestion and detours in later stages.