Clock Skew vs Clock Latency

• Clock skew is the difference in clock arrival times at the various clocked elements.
• Clock latency is the delay for the clock to travel from where it is generated to the clock input pin, from which it is then distributed to the individual flops.

KEY Skew is the arrival-time difference between flops; latency is the source-to-clock-pin delay.

Clock Tree Synthesis (CTS)

• Clock tree synthesis balances clock skew and minimises insertion delay so that timing, power and other constraints are met.

CTS provides several features to help achieve timing closure:

• Global-skew clock tree synthesis.
• Local-skew clock tree synthesis.
• Real-clock useful-skew clock tree synthesis.
• Ideal-clock useful-skew clock tree synthesis.
• Interlock delay balancing.
• Splitting a clock net to replicate clock-gating cells.
• Clock tree optimization.
• High-fanout net synthesis.
• Concurrent multi-corner (worst- and best-case) clock tree synthesis.
• Concurrent multi-clock synthesis with domain overlap.