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VLSI Physical Design  ›  Ch 2. Floorplanning & Die

resource ratio is roughly 2:1.8 - giving slightly less vertical routing and a chip that is wider than it is tall.

  • Using that resource ratio, the best aspect ratio works out to about 1.11, making the chip rectangular and wider than tall.
  • In a four-layer design, metal1 is unusable and metal2 is about 20% via-obstructed, while metal3 (horizontal) and metal4 (vertical) are fully available. This leaves about 80% more vertical than horizontal routing resource, an H-to-V ratio near 0.56, so the chip is taller than it is wide.

KEY Assume ~70% cell utilization; aspect ratio follows the horizontal-to-vertical routing-resource balance.

Halo vs Blockage

A block halo (keep-out margin) can be applied around hard macros, black boxes or committed partitions. Once added, the halo becomes a property of the block, so moving the block moves the halo with it.

A blockage can be placed on any part of the design, but it does not move when a block is moved.

KEY A halo sticks to its block and moves with it, a blockage stays put when blocks move.

Typical Utilization Values

There is no strict rule, but maintaining roughly these targets usually lets the design close without major congestion:

  • Floorplan - about 70%.
  • Placement - about 75%.
  • CTS - about 80%.
  • Routing - about 85%.
  • At GDSII generation - 100% (filled completely).

KEY Typical utilization climbs ~70% floorplan, ~75% placement, ~80% CTS, ~85% routing, 100% at GDSII.