Partitioning

Partitioning is the process of splitting a design into manageable pieces so that complex components can be implemented more easily. During this step, the timing and physical implementation models are defined. The floorplan created during prototyping is pushed down into the lower-level blocks, preserving placement, power routing and obstructions related to placement and routing. Feedthroughs may also be assigned for nets routed over a block and buffered using hole-punch buffers or by modifying the block netlist. Logical partitioning is not needed for flat physical implementations.

Partitioning splits the design for logical and physical implementation; in hierarchical flows, the logical partitioning directly affects the physical implementation phase.

It is a way to manage functional complexity from a logical-design perspective, and it lets multiple design teams work in parallel.

The bridges between flat and hierarchical physical implementation are: creating timing budgets, pin optimization, feedthrough or hole-punch buffer assignment, floorplan push-down of obstructions and power routes, and advanced netlist optimization for timing, clock, power and signal integrity.

KEY: Partitioning divides a design into manageable blocks for parallel work, pushing the floorplan and budgets down into each block.

Hierarchical vs Flat ASIC Design

Flat design - advantages:

• There are no boundary-constraint problems between hierarchy levels.
• You can analyse IO-to-block and hard-macro-to-block paths, and timing is more accurate because no block modeling is required.

Flat design - disadvantages:

• Large data sizes and potentially long run times.

Hierarchical design - advantages:

• Timing can be closed at the top level and the block level in parallel, saving time.
• Early top-level timing analysis is possible.