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VLSI Physical Design  ›  Ch 1. PD Flow & Fundamentals

The same idea applies to repeaters. Long-distance routing means a large RC load from a series of RC delays, so splitting the line into several pieces with repeaters helps - because the gate delay of a repeater is small compared with the RC delay.

  • For an interconnect driven by a single inverter, the propagation delay is roughly Tdelay = tgate + n x R x n x C = tgate + n^2 x RC.
  • If two repeaters are inserted, the delay becomes Tdelay = tgate + 2 x tgate + 3RC = 3 tgate + 3RC, showing how the RC term shrinks.

If the gate delay is much smaller than the RC delay, repeaters improve switching speed at the cost of higher power. As you add repeaters to a fixed-length net, the total delay falls, but at some point the gate delay dominates the net delay; adding repeaters beyond that sweet spot makes the total delay rise again, so you should not exceed it. This is how the net length a given buffer can drive is determined.

KEY: Splitting a net with buffers reduces its quadratic RC delay, but only up to the sweet spot where gate delay starts to dominate.

Top-Down vs Bottom-Up Design Flows

  • The priority of the flow is overall design closure.
  • Data flows from the top level down to the blocks.
  • Feedback flows from the blocks back up to the top.

From the top, the blocks receive the initial die shape and the initial port placement.

Back to the top, the blocks return the final design shape and the final port placement.

KEY: Top-down passes die shape and port placement down; bottom-up feeds the finalized shape and ports back up for closure.

Why Incremental Optimization Helps

  • Incremental optimization is essentially re-optimising an already optimised design.
  • Running it makes the tool re-examine the current worst paths based on the new timing histogram.