JTAG

Answer 1:

• JTAG stands for Joint Test Action Group. It is also the IEEE 1149.1 standard for a Standard Test Access Port and Boundary-Scan Architecture, and it is one of the DFT techniques.

Answer 2:

• JTAG boundary scan is a method for testing ICs and their interconnections. It uses a shift register built into the chip so inputs can be shifted in and the resulting outputs shifted out. JTAG needs four IO pins: clock, input data, output data and state-machine mode control.
• JTAG's use later expanded to debugging software on embedded microcontrollers, removing the need for costly in-circuit emulators, and it is also used to download configuration bitstreams into FPGAs.
• JTAG cells, also called boundary-scan cells, are small circuits placed just inside the IO cells to move data to and from the IO through the boundary-scan chain. The interface to these chains is the TAP (Test Access Port), and both the chains and the TAP are controlled by an on-chip JTAG controller.

KEY: JTAG (IEEE 1149.1) is a boundary-scan DFT standard using a TAP and four IO pins to test, debug and program chips.

Timing Violations in a Report

• Setup time violations.
• Hold time violations.
• Minimum delay violations.
• Maximum delay violations.
• Slack.
• External delay.

KEY: A timing report shows setup, hold, min-delay, max-delay, slack and external-delay violations.