and clock nets still need attention.

Logic synthesis does not balance high-fanout nets or clock nets, so a single clock port may drive thousands of flops with only a virtual route. CTS is the stage that turns this into a balanced tree with minimum skew and latency.

Until clock synthesis (CTS) is finished you cannot route. After CTS you route the clock nets first, then the data signals.

KEY Clocks are ideal/unbalanced until CTS - route only after CTS, clocks first then data.

Timing on Clock-Gating Paths

• While building the clock tree, all flops are balanced, which makes the clock-gate cell arrive early in the tree by its own delay. The time available to meet setup at the gating element then becomes the clock period minus that delay - a tighter window.
• If the clock gate's fanout exceeds its drive capability, a small extra buffer tree appears, making the clock arrive at the gate even earlier and tightening the setup requirement further.

KEY Clock-gate cells arrive early in the tree, shrinking the setup window below a normal flop-to-flop path.

Inverter on the Capture Clock Pin

• Before the inverter is added, the path has a full clock cycle available for setup.
• After insertion it becomes a half-cycle path for setup, so setup timing turns very critical. Hold, however, is relaxed: the capture clock now arrives half a period earlier (on the negative edge) while the launch clock comes on the positive edge, giving the hold path an extra half cycle and making it less critical.

KEY An inverter on the capture clock makes setup a tight half-cycle path but relaxes hold by half a cycle.