Tie-High and Tie-Low Cells TIEH and TIEL cells protect cells from ESD. Cell input pins that need a constant logic value are connected to a TIEH or TIEL cell instead of directly to the power or ground rail. If those input pins were tied directly to PG, the cells could be damaged by any power-supply fluctuation - the tie cells provide a safe, buffered connection to the required logic level. KEY Tie-high/tie-low cells safely supply a constant logic value to input pins, protecting cells from ESD and supply fluctuations.

Dynamic Power Without Architecture Changes Options include using multibit flops, applying clock gating, adding XOR self-gating on ungated registers, doing power-aware placement driven by a SAIF file, reducing insertion delay, and avoiding unnecessarily large uncertainty values. KEY Cut dynamic power with multibit cells, clock gating, self-gating, SAIF-based placement and lower insertion delay.

Fixing Dynamic Voltage (IR) Drop

• Make the power grid denser by adding extra power and ground straps to improve current conduction.
• Apply cell padding to cells that switch simultaneously, reducing the peak current they pull from the grid.
• Downsize cells on non-critical paths to lower their instantaneous current demand at local hotspots; the set_clock_cell_spacing command can spread out high-activity clock cells, effectively shifting the timing window of non-critical cells.
• Insert decap cells, which act as a charge reservoir supplying current during simultaneous switching in a hotspot - though decaps are leaky and add to leakage power.
• Split the output capacitance, since current drawn from the grid is proportional to the load being driven; load splitting lowers the peak current demand.
• Use MIM (Metal-Insulator-Metal) capacitors to stabilize the power