• Capacitance must be defined for all four cases: rise, fall, min and max.
• Insertion delay is normally supplied in the .lib or .db.
• If insertion delay is not defined, timing violations appear when the macro is flattened during STA.
• A relevant question to consider: should the block-level insertion delay be greater than the macro insertion delay?

KEY A macro model supplies clock insertion delay, pin transition/load, and rise/fall/min/max capacitance.

Time Borrowing

Time borrowing (also called cycle stealing) is taking time from the next clock cycle, and it happens with latches rather than edge-triggered flip-flops.

Because a latch stays transparent while its clock is enabled (unlike a flip-flop that changes only on an edge), a slow path can extend into the latch's open window and finish later. For example, with a 5ns clock and a 6ns path, replacing the source flip-flop with a latch lets the path borrow up to half a period (2.5ns) from the next cycle, turning a 1ns overrun into positive slack.

KEY Time borrowing lets a slow path extend into the next cycle's window using a transparent latch.

Characteristics of Time Borrowing

• Time borrowing can span multiple stages.
• Both launch and capture must use the same phase of the same clock - if they are out of phase, borrowing is disabled.
• It must be contained within the same clock cycle.
• It slows down the effective data arrival time.
• It affects the setup slack calculation.
• It does not affect hold slack, because hold checks use the fastest data.