If data reaches L2 before PH2 opens at time=10, the next path L2 to L3 is launched by PH2's opening edge at time=10, just like a synchronous flop (Setup 2a). If data arrives after PH2 opens, the first path borrows time from the second: the launch for L2 to L3 occurs at the actual data-arrival time at L2, somewhere between PH2's opening and closing edges (Setup 2b). When borrowing happens the path starts at the D pin of L2 rather than its G pin. For the L1-to-L2 path the timing engine reports zero setup slack when borrowing occurs, positive slack if data arrives before the opening edge at time=10, and negative slack (a violation) if it arrives after the closing edge at time=20. For hold checking, the timing engine considers the launch and capture edges relative to the setup check and verifies that data launched at the start point does not reach the endpoint too quickly, ensuring previously launched data is not overwritten.

KEY Yes - STA analyzes latch-based designs using time borrowing across two-phase non-overlapping clocks.

Cell Delay and Net Delay Gate delay (also called cell delay):

• Gate delay is a function of the input transition time and the total output load (Cnet + Cpin).
• For any gate it is measured from the 50% point of the input transition to the corresponding 50% point of the output transition. Intrinsic delay:
• Intrinsic delay is the delay internal to the gate, from its input pin to