• Certain setup checks involving transparent latches.

There is an important difference between hold and setup analysis regarding crosstalk on the common clock path. For hold, the launch and capture clock edge are normally the same edge, so the common clock portion cannot have different crosstalk contributions for the launch and capture paths - therefore worst-case hold analysis removes the crosstalk contribution from the common clock path.

For setup analysis, launch and capture occur on different clock edges separated by one clock period, so the crosstalk contributions on the common clock path differ between the launch and capture paths. Therefore the crosstalk contribution should not be removed from the common clock path for setup.

KEY CRPR removes common-path crosstalk pessimism only for zero-cycle (hold) checks; for setup, launch and capture differ, so it is kept.

Different Derates for Clock and Data Cells

• Clock cells switch far more than data cells, so they can cause more PVT variation; clock-cell delay shifts from OCV can therefore produce many more violations than the data path, which is why clock cells get more derating than data cells.
• The OCV effect is typically more pronounced on clock paths because they travel longer distances across the chip.
• Clock cells exhibit second-order effects, so their derates are larger, while data cells exhibit first-order effects and need less derating.

KEY Clock cells switch more, travel farther and show second-order effects, so they get larger derates than data cells.

Frequency vs Uncertainty for Over-Constraining

Adjusting the clock frequency is better because it changes how the crosstalk arrival windows are computed. The tool can then see those crosstalk effects and fix them appropriately without over-fixing, and the silicon success rate is higher.

Changing the uncertainty does not affect the crosstalk arrival-window