clock-path delay minus capture clock-path delay.

Solutions - correct the skew problem:

• Reduce the clock-path delay of each launching register according to its violation; apply a float-pin on the start-point CLK pin with a positive value equal to the violation.
• Use the appropriate commands, such as get_timing_paths, to identify and drive the fix.

Endpoint-based fixing:

• Endpoints are fewer in number, so the fix is more contained.
• Margin must be maintained at the register driven by the clock gater.

KEY Clock-gating violations are skew problems fixed by trimming launch clock delay or endpoint-based fixing.

Large Insertion Delay vs More Skew

The block timing is better in case 1. But the decision depends on full-chip timing and total cell utilization at the opt-CTS stage.

If case 1 has high latency, minimum skew and good block timing, you should still check full-chip timing for that case; if it is also good and the incremental opt-CTS utilization is not much different from case 2, then case 1 is acceptable - otherwise choose case 2.

Practically, if two-tile and one-tile full-chip timing are comparable, check the total utilization at opt-CTS (the incremental clock-cell area added at CTS); if that area is small, the lower-area option is fine, but the full-chip one-tile versus two-tile timing should be checked first.

If timing differences exist, the ECO stage will end up doing skew work or using useful skew to fix timing, and power will be higher in that case anyway. If timing is met, you can do VT-swap to recover power. The overall preference is to prioritize timing first, then address power.

KEY Prefer the low-skew DB if full-chip timing and opt-CTS utilization hold up - prioritize timing, then recover power.