Sources of Pre-CTS Clock Skew

Skew at pre-CTS comes mainly from in-die process, voltage and temperature (PVT) variation:

• Different clock buffers having different channel lengths.
• Local voltage drop, which increases buffer delay.
• Hot spots, which increase gate and wire delay.
• Device mismatch across the die.

KEY Pre-CTS skew comes from in-die PVT variation: buffer channel-length spread, local IR drop, hotspots and device mismatch.

Jitter and Its Sources

Clock jitter is the inaccuracy in clock-edge position introduced by the clock-generation circuitry relative to an ideal clock; it can be viewed as a statistical variation in clock period or duty cycle.

Sources of clock jitter include:

• Temporal power-supply variation - changing activity alters the supply voltage from cycle to cycle, affecting global or local clock buffers.
• PLL jitter - supply variation at the PLL shifts the oscillator frequency, PLL components have non-zero response time, reference-clock jitter gets multiplied by the PLL, and supply noise in the global clock distribution makes the feedback clock appear to jitter.
• Wire coupling - changing data alters coupling from cycle to cycle.
• Dynamic de-skewing circuitry.

KEY Jitter is clock-edge variation from supply noise, PLL behavior, wire coupling and de-skew circuitry.

Clock Buffer vs Regular Buffer

Clock buffer advantages:

• Equal rise and fall transition times, because the PMOS and NMOS have matched on-resistance - achieved by making the PMOS width about 2.5 times the NMOS width.
• It preserves the pulse width of the clock signal.