the power management block to clamp the output and block the unknown value.

KEY Isolation cells clamp signals crossing from a switchable to an AON domain - AND clamps to 0, OR clamps to 1.

Drawing NAND and NOR with CMOS

A CMOS NAND gate uses two PMOS transistors in parallel for the pull-up network and two NMOS transistors in series for the pull-down network.

A CMOS NOR gate uses two PMOS transistors in series for the pull-up network and two NMOS transistors in parallel for the pull-down network.

KEY NAND = parallel PMOS, series NMOS, NOR = series PMOS, parallel NMOS.

Equal PMOS and NMOS in a Transmission Gate

A transmission gate uses transistors as switches between driving and load circuits, transmitting information from one circuit to another. The applied bias decides which terminal acts as the drain and which acts as the source.

NMOS transmission gate: with the gate at a variable Vg, one terminal at the input Vin and the other at the load CL, the output is taken