KEY CTS builds the clock network, balancing skew and minimising insertion delay to meet timing and power.

SDC Constraints for the Clock Tree

• CTS will not run if the SDC has no create_clock statements, so the SDC must contain at least one. If create_clock is defined on a pin that does not physically exist (only in the hierarchical netlist), CTS also cannot run.
• It is good practice to also define set_clock_transition, set_clock_latency and set_clock_uncertainty.

CTS observes the following clock-tree constraints:

• Maximum transition delay.
• Maximum load capacitance.
• Maximum fanout.
• Maximum buffer level.

KEY CTS needs create_clock plus transition/latency/uncertainty constraints, and honours max tran, cap, fanout and buffer levels.

Number of Buffer Levels in CTS

The number of buffer levels is governed by the clock-tree constraints and is managed alongside placement and routing-resource adjustments such as:

• Spreading the macros.
• Spreading the standard cells.
• Increasing strap width.
• Adding more straps.
• Applying proper blockages.

KEY Buffer levels are set by the clock-tree constraints, supported by spreading cells/macros and tuning power resources.