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VLSI Physical Design  ›  Ch 8. Corners, Derates & OCV

Chapter 8

Corners, Derate, OCV & Timing Closure

Derate Values

  • For setup checks: derate the data path by about 8-15%, with no derate on the clock path.
  • For hold checks: derate the clock path by about 8-15%, with no derate on the data path.

KEY Roughly 8-15% derate - on the data path for setup, on the clock path for hold.

Sign-Off Corners

  • Corners checked: worst, best and typical.
  • The derate value is the same for best and worst, for the typical corner it can be smaller.

KEY Sign off at worst/best/typical corners; typical can use a lower derate.

Source of Wire Load Models

  • Wire load models (WLMs) are supplied by the library vendor.
  • We do not create WLMs ourselves.
  • They are specified based on the block area.

KEY WLMs come from the library vendor and are selected by area - we don't create them.

Source of the Derating Value

  • The derating value is set from library-vendor guidelines combined with experience from previous designs.
  • PVT variation (process, voltage, temperature) is the underlying factor that drives the derating factor.

KEY Derate comes from vendor guidance plus experience; it accounts for PVT variation.