Random-Access Memory (RAM)
Memory where any word can be read or written in the same time, by its address.
Description
RAM is an array of words that supports read and write in constant time regardless of address. An address selects one word through a decoder; control lines choose read or write; data moves on a shared data bus. SRAM uses latches (fast, bulky); DRAM uses one capacitor per bit (dense, needs refresh).
- Each word has a unique address; m address bits select 2^m words.
- Write: place address + data, assert write — the word is overwritten.
- Read: place address, assert read — the word appears on the data bus.
- Access time is independent of which address (hence 'random access').
- Control: chip-enable + read/write lines.
- SRAM: a latch per bit — fast, no refresh, but ~6 transistors/bit.
- DRAM: one capacitor + transistor per bit — dense, but leaks → needs refresh.
- Caches use SRAM; main memory uses DRAM.
- Capacity = 2^(address bits) words × bits/word.
- A 1K×8 RAM needs 10 address lines and 8 data lines.
At a glance
What
An addressable array of words supporting read and write, with equal access time for any address.
Why
Programs need fast scratch storage that can be both read and written at will.
How
Address → decoder → one word line; read/write control gates data on/off the data bus.
Where
CPU caches (SRAM), main memory (DRAM), buffers.
When
Any time data must be stored and changed during operation.
Operation
- Each word has a unique address; m address bits select 2^m words.
- Write: place address + data, assert write — the word is overwritten.
- Read: place address, assert read — the word appears on the data bus.
- Access time is independent of which address (hence 'random access').
- Control: chip-enable + read/write lines.
SRAM vs DRAM
- SRAM: a latch per bit — fast, no refresh, but ~6 transistors/bit.
- DRAM: one capacitor + transistor per bit — dense, but leaks → needs refresh.
- Caches use SRAM; main memory uses DRAM.
- Capacity = 2^(address bits) words × bits/word.
- A 1K×8 RAM needs 10 address lines and 8 data lines.
Read / Write control
| CE | R/W | Operation |
|---|---|---|
| 0 | x | disabled (Hi-Z) |
| 1 | 1 | Read word[addr] |
| 1 | 0 | Write data → word[addr] |
SRAM vs DRAM
| SRAM | DRAM | |
|---|---|---|
| Cell | latch (~6T) | 1T + 1C |
| Speed | fast | slower |
| Refresh | no | yes |
| Use | cache | main memory |
Black-box view
Inputs on the left → outputs on the right · particles show signal direction
Functional / block diagram
Functional blocks · arrows animate in the direction data flows
RAM — address, read, write
▶ live simulatordecoder→ row 0
8×4 RAM · address decoder selects one word · Write stores, Read fetches
HDL — Verilog · VHDL · SystemVerilog
module ram #(parameter AW=8, DW=8)
(input clk, we,
input [AW-1:0] addr,
input [DW-1:0] din,
output reg [DW-1:0] dout);
reg [DW-1:0] mem [0:(1<<AW)-1];
always @(posedge clk) begin
if (we) mem[addr] <= din;
dout <= mem[addr];
end
endmoduleSynchronous RAM inference — synthesizes to a block-RAM on FPGAs.
Real-world applications
The 5 Whys
- 1
Why random access? Any word must be reachable equally fast.
- 2
Why a decoder? Turns m address bits into one of 2^m word selects.
- 3
Why SRAM for cache? Latches are fast and need no refresh.
- 4
Why DRAM for main memory? Capacitor cells are far denser/cheaper.
- 5
Root cause: addressable arrays give large, uniform-latency read/write storage.
Cheat sheet
Working principle
- Address → decoder → one word line; read/write control gates data on/off the data bus.
- An addressable array of words supporting read and write, with equal access time for any address.
Formulas & Boolean expressions
- Capacity = 2^m words × n bits
- Address lines = m, Data lines = n
- Each word has a unique address; m address bits select 2^m words.
- Capacity = 2^(address bits) words × bits/word.
Key facts
- Each word has a unique address; m address bits select 2^m words.
- SRAM: a latch per bit — fast, no refresh, but ~6 transistors/bit.
Why it exists
- Root cause: addressable arrays give large, uniform-latency read/write storage.