KEY The 500 MHz clock is harder - its shorter period makes it more tightly constrained.

Double Spacing and Vias for the Clock

• The clock is targeted because it switches regularly and more often than any other signal; if another signal also switches fast, double spacing can be applied to it as well.
• Double spacing increases the effective width, lowering capacitance and therefore crosstalk.
• Multiple vias place resistances in parallel, reducing resistance and hence RC delay.

KEY The clock switches the most, so double spacing cuts its crosstalk and multiple vias cut its RC delay.

Clock-Gate Enable Paths After CTS

After CTS, clock gates become critical because, by default, their clock-pin arrival time is given the same latency as the register clock pins. Once the clock tree is built, clock gates sit in the intermediate part of the tree, not at the leaf, so their clock arrives earlier than at the leaf clock pins, which hurts timing.

• Pre-CTS, the register pins and the clock-gate clock pins both see a clock latency of 0ns, so their arrival times are modeled the same.
• Post-CTS, a clock gate halfway down the tree might see a latency of 800ps, while the leaf-level registers see a 1.5ns clock arrival time.
• Any path from a register to that clock gate now sees the arrival-time difference, so the pre-CTS slack is degraded by about 700ps (1.5ns minus 800ps). Since clock gates are meant to be at an intermediate point to allow shutting down parts of the tree, it is wrong to assume their clock pins should be balanced with the registers.

These paths can be handled as follows:

• First, check how far down the clock tree the ICGs sit post-CTS - being near the root or near the leaf clock pins changes how you treat them.