downsize the driven cell.

• Max fanout - reduce fanout by load splitting, buffering or cloning.

KEY DRVs = max tran/cap/fanout, caused by weak drivers, long nets and high load; fix with sizing, buffering, load splitting.

Path Groups

A path group is simply a group of timing paths. Grouping guides where the synthesis/optimization engine spends its effort.

If every path is in one group, the engine spends most time on the worst violators and moves on only after each meets timing.

Grouping lets you separate paths that need an architectural change (so the tool does not waste effort on them) and paths that were starved of optimization, giving each set its own priority.

KEY Path groups steer the optimizer's effort by priority instead of chasing only the worst violator.

Separate Path Groups for IO Paths

Path groups are the foundation of the optimization cost function, so more realistic groups make it easier for the tool to reach an optimal result everywhere.

IO constraints are usually budgeted rather than exact and may not be clean from a clock-domain view. Kept with internal paths, they distort the quality of results - and because the tool works on the most critical path first, a critical IO path can starve internal paths and give a sub-optimal design.

KEY Separating IO paths stops their budgeted, noisy constraints from starving internal-path optimization.

Finding a False Path

A false path is a timing path that does not need to be optimised because it can never be required to capture within a limited time during normal chip operation.

Normally a signal launched from one flop must be captured at another within a single clock cycle. But in some scenarios the arrival