Hold and Frequency

• For full-cycle timing paths hold does not depend on frequency, because the launch and capture edges arrive at the same time.
• For half-cycle timing paths hold does depend on frequency, because the launch and capture edges arrive at different times.

KEY Hold is frequency-independent for full-cycle paths but frequency-dependent for half-cycle paths.

Fixing a Half-Cycle Path

On a half-cycle path the hold check becomes easy to satisfy, but the setup check turns critical because only half a clock period is available for the data to arrive.

KEY Half-cycle paths make hold easy but setup critical due to the shortened window.

Timing Window vs Design Frequency

A timing window is the gap between the maximum and minimum arrival times on a timing arc. Because those arrival times depend on the clock period, the timing window shifts whenever the frequency is changed.

KEY Timing window = max minus min arrival time, and it shifts when frequency changes.

Threshold Voltage and Propagation Delay

Threshold voltage is the minimum gate voltage needed to form a conducting channel between the source and drain of a CMOS transistor. Cell delay is inversely proportional to the threshold voltage - a lower Vt gives a faster cell.

KEY Vt is the voltage needed to form the channel; cell delay is inversely proportional to Vt.