loads on spine and root, so the tool needs a range of cells to work with, otherwise it over-inserts high-drive cells.

KEY Use proper-strength clock inverters, double-width nets, central gating, multi-point or mesh CTS, and keep congestion low before CTS.

Increasing Clock Slew Pre-CTS

Applying a clock transition constraint on clock pins before CTS is a way of modelling the clock-to-Q delay and the flop's library setup check up front, instead of waiting until after CTS. In effect it models the library setup margin that you would otherwise see only after CTS. The library setup requirement on the flops increases (it depends on both the clock-pin slew and the data-pin slew), so less of the clock period is left for the data path and the tool has to work harder to close timing.

KEY It models the post-CTS library setup margin early - the flop setup requirement rises, leaving less time for the data path.

Multiple Clocks Through a MUX

• Build a real clock tree for the functional clock - the one entering the MUX D0 pin - from its functional clock port to all the register pins.
• Apply set_dont_touch_network on the MUX output (Z) pin, then build CTS for the test clock.
• Build a DRC-only clock tree on the test clock that feeds the MUX D1 pin, routing it only up to the D1 pin.

KEY Build a full tree for the functional clock through D0, dont-touch the MUX output, and a DRC-only tree for the test clock up to D1.