Steps to Solve a Setup or Hold Problem

• Draw the waveforms for the launch and capture clocks.
• If no skew is given, draw the clocks as ideal clocks.
• Mark the active edges of the launch and capture clocks.
• Mark the setup checks, which are one cycle apart.
• Mark the hold check, which is taken between the current launch active edge and the previous capture active edge.

KEY Draw launch/capture waveforms, mark active edges, then mark the setup (1-cycle) and hold checks.

Closing Setup Timing Violations

• Examine the clock skew first.
• Optimise the data path before touching the clock.
• Look at adjusting clock skew, using a float-pin constraint or useful skew.
• Useful skew at the launch flop: trade off against the timing margin available into that launch flop.
• Useful skew at the capture flop: trade off against the timing margin available out of that capture flop.

KEY Check skew, fix the data path first, then apply useful skew within available margin at launch or capture.

Valid Timing Start Points

• An input port.
• The clock pin of a flip-flop.

KEY Valid start points are input ports and flop clock pins.

Valid Timing Endpoints

• An output port.
• The data (D) pin of a flip-flop.

KEY Valid endpoints are output ports and flop D pins.