KEY Worst delay = maximum delay; best delay = minimum delay of a gate or net.

Delay Models for Estimation

• Wire load model.
• Elmore delay model.
• Lumped capacitor model.
• Lumped RC model.
• Distributed RC model.
• RLC model.
• Transmission line model.

Whatever delay model is chosen applies to every cell in that library - multiple delay models cannot be mixed within a single library.

KEY Models: WLM, Elmore, lumped-C, lumped-RC, distributed-RC, RLC, transmission line - one per library.

Static Sensitization

A path is statically sensitized when all side inputs along it hold their non-controlling values (for an AND gate the controlling value is 0, non-controlling is 1). Static sensitization is sufficient for a path to be a true path.

A path is statically co-sensitized if the path input is consistent with the value at the output of each gate on the path; in a co-sensitized path, if the path input is controlling, the side inputs may also be sensitizing.

KEY A path is statically sensitized when all side inputs hold non-controlling values - making it a true path.

Metastability

If a flip-flop's setup or hold time is violated, it can enter an unpredictable metastable (quasi-stable) state, which can cause system failure in FPGAs, ASICs and similar devices.

In the metastable state the circuit cannot settle to a clean logic 0 or 1 within the required time, breaking functionality. It happens when the