Tape-Out With One Transition Violation

No - a design should not be taped out until all logical DRCs and timing issues are resolved, because a transition violation affects functionality, the power budget and the timing budget.

• Effect on functionality - it degrades the cell's noise margin, because the load capacitance may not charge fully to VDD during a low-to-high or high-to-low transition at the cell input.
• Effect on power budget - the pull-up and pull-down networks can be on simultaneously, creating a short-circuit current straight from VDD to VSS; this short-circuit power dissipation can cause the design to miss its power-budget spec.
• Effect on performance and timing - the bad input slew forces the timer to compute cell delay from the liberty table by extrapolation rather than interpolation, which is less accurate and adds pessimism, since no proper delay-table boundary exists for the violated condition even with statistical or parametric STA methods.

KEY No - a transition violation breaks noise margin, burns short-circuit power, and forces pessimistic extrapolated timing.

The DEF File and Its Use

DEF (Design Exchange Format) describes the physical side of a design:

• Physical aspects such as die size, connectivity and macros.
• Floorplanning information such as standard cells, placement and routing.
• The physical representation of power and signal routing, pins, and so on.

KEY DEF captures the physical design - die size, floorplan, placement, routing and pins.

Checks Done in PrimeTime

• Timing - setup, hold and transition.
• Design constraints.
• Nets.
• Noise.