flip-flop is toggling during the clock transition - i.e. setup/hold is violated and the flop output is left indeterminate.

KEY Metastability is a flop stuck between 0 and 1 after a setup/hold violation.

Reasons for Metastability

• Slow input/output transition times (rise and fall time).
• Low VDD.
• High parasitic capacitances.
• Crosstalk.
• An asynchronous input signal.
• High clock skew.
• Excessive combinational delay.

KEY Causes: slow slews, low VDD, high parasitics, crosstalk, async inputs, high skew, long logic delay.

Avoiding or Tolerating Metastability

If input data meets setup and hold constraints, metastability is largely reduced; it is hardest to control when signals come from different clock domains.

• Keep the clock period precise to avoid delay.
• Add one or more successive synchronizing flip-flops to the synchronizer.
• Use metastability-hardened flip-flops.
• Provide enough settling time.
• Receive each asynchronous signal by clocking it into only one flip-flop.
• Use asynchronous reset.
• Use a metastability filter, though it increases slack.

KEY Tame metastability with synchronizers, hardened flops, settling time and single-flop async capture.