Volume II: Digital Logic › Combinational Logic

Multiplexers

A data selector: routes one of several inputs to the output based on select lines.

On this page:Description At a glance Theory Black-box view HDL Applications 5 Whys Cheat sheet

Description

A circuit that forwards one chosen input to a single output. It shares one resource/bus among many sources and implements logic compactly. Select lines enable exactly one input path to the output.

n select bits choose among 2ⁿ data inputs.
A MUX can implement any function by feeding constants/literals to its inputs.
Demultiplexers do the reverse: one input to one of many outputs.
What: A circuit that forwards one chosen input to a single output.
Why: It shares one resource/bus among many sources and implements logic compactly.
How: Select lines enable exactly one input path to the output.
Where: Buses, ALU operand selection, FPGA logic (LUTs are MUX-based).
When: Any time one of several signals must be chosen at runtime.
Analogy — A multiplexer is a railway switch: many tracks (inputs) feed in, the lever (select lines) picks exactly one to continue down the single output track.

At a glance

What

A circuit that forwards one chosen input to a single output.

Why

It shares one resource/bus among many sources and implements logic compactly.

How

Select lines enable exactly one input path to the output.

Where

Buses, ALU operand selection, FPGA logic (LUTs are MUX-based).

When

Any time one of several signals must be chosen at runtime.

Think of it like…

A multiplexer is a railway switch: many tracks (inputs) feed in, the lever (select lines) picks exactly one to continue down the single output track.

Selection

n select bits choose among 2ⁿ data inputs.
A MUX can implement any function by feeding constants/literals to its inputs.
Demultiplexers do the reverse: one input to one of many outputs.

4-to-1 MUX

S1	S0	Output Y
0	0	I0
0	1	I1
1	0	I2
1	1	I3

Black-box view

Inputs on the left → outputs on the right · particles show signal direction

4-to-1 multiplexer

▶ live simulator

Select = 00 (0) → routes D0 to Y. Click any D or S to toggle.

HDL — Verilog · VHDL · SystemVerilog

module mux4(input [3:0] d, input [1:0] sel, output reg y);
  always @(*)
    case (sel)
      2'b00: y = d[0];
      2'b01: y = d[1];
      2'b10: y = d[2];
      2'b11: y = d[3];
    endcase
endmodule

4-to-1 MUX three ways: case, indexed select, and a conditional dataflow form.

Real-world applications

On-chip & memory busesALU operand / result selectionFPGA logic (LUT = MUX tree)Time-division data serializationClock/signal source selection

The 5 Whys

1
Why a multiplexer? To choose one of many signals onto a shared line.
2
Why share a line? Wires and ports are limited resources.
3
Why is it universal? Driving its inputs with constants realizes any function.
4
Why do FPGAs love MUXes? LUTs are essentially MUX trees.
5
Root cause: runtime selection is a core need, and a MUX is its minimal primitive.

Cheat sheet

Working principle

Select lines enable exactly one input path to the output.
A circuit that forwards one chosen input to a single output.

Formulas & Boolean expressions

n select bits choose among 2ⁿ data inputs.

Key facts

n select bits choose among 2ⁿ data inputs.

Why it exists

Root cause: runtime selection is a core need, and a MUX is its minimal primitive.