• It was once assumed the clock buffer is faster than a regular buffer because a regular buffer has roughly 2.5x the NMOS resistance; in practice, however, a clock buffer actually has slightly more delay than a regular buffer. Clock buffer disadvantages:
• Larger area than a regular buffer, due to the wider PMOS - an area penalty.
• Higher leakage current because of the lower PMOS on-resistance, so leakage power is greater with clock buffers.

KEY Clock buffers give equal rise/fall and preserve pulse width, but cost more area and leakage than regular buffers.

Jitter and Hold Violations

Jitter is the time variation of a periodic signal. Since hold is checked on the same clock edge - the launch and capture edges of the same edge - jitter does not affect hold violations as long as there is no uncommon clock path. If the launch and capture clocks share an uncommon path, distribution jitter on that path can affect hold.

KEY Jitter does not affect hold unless there is an uncommon clock path between launch and capture.

Jitter and Setup Violations

Yes - jitter affects setup violations, because setup is checked across the clock edges of the launch and capture flops, which are different edges and therefore subject to jitter.

KEY Jitter affects setup because the launch and capture checks use different clock edges.

Useful Skew

• It is used when there is no further room to optimise the data path.

Useful skew on the launch path:

• Useful when many start points need their clock to arrive earlier.
• Sometimes it is hard to make the launch clock earlier because doing so can violate transition limits.