Volume II: Digital Logic › Register Transfer Level Design

HDL Description of Binary Multiplier

The full add-and-shift multiplier coded as controller + datapath HDL.

On this page:Description At a glance Theory HDL Applications 5 Whys Cheat sheet

Description

The sequential multiplier codes as a controller FSM (idle → load → add/shift loop → done) and a datapath ({A,Q} shift-accumulator, adder, counter). The controller asserts add/shift/load and reads the counter-zero status; the datapath performs the add-and-shift transfers.

State machine: IDLE, LOAD, ADD, SHIFT, DONE.
Datapath: A accumulator, Q multiplier, B multiplicand, P counter.
ADD state: if Q0, A <= A + B.
SHIFT state: {A,Q} <= {A,Q} >> 1; P <= P - 1.
Loop until P = 0, then DONE.
Non-blocking assignments for all registers.
Concatenate {A,Q} for the combined shift.
Counter-zero is the loop-exit status.
Reset → IDLE with cleared registers.
Mirror the ASMD chart exactly.

At a glance

What

Synthesizable HDL for the add-and-shift multiplier.

Why

It realizes the ASMD multiplier design in hardware.

How

Controller FSM + {A,Q} datapath with one adder and a counter.

Where

ALU multiply units.

When

Implementing a sequential multiplier.

Think of it like…

Two coordinated scripts again: the FSM calls 'add', 'shift', 'check counter'; the datapath performs each on cue until the product is built.

Structure

State machine: IDLE, LOAD, ADD, SHIFT, DONE.
Datapath: A accumulator, Q multiplier, B multiplicand, P counter.
ADD state: if Q0, A <= A + B.
SHIFT state: {A,Q} <= {A,Q} >> 1; P <= P - 1.
Loop until P = 0, then DONE.

Coding notes

Non-blocking assignments for all registers.
Concatenate {A,Q} for the combined shift.
Counter-zero is the loop-exit status.
Reset → IDLE with cleared registers.
Mirror the ASMD chart exactly.

States

State	Action
LOAD	A←0, load B,Q,P
ADD	if Q0: A←A+B
SHIFT	shr {A,Q}; P←P−1
DONE	product in {A,Q}

HDL — Verilog · VHDL · SystemVerilog

always @(posedge clk) begin
  if (rst) begin state<=IDLE; A<=0; end
  else case (state)
    IDLE:  if (start) begin A<=0; P<=N; state<=TEST; end
    TEST:  state <= Q[0] ? ADD : SHIFT;
    ADD:   begin A <= A + B; state<=SHIFT; end
    SHIFT: begin {A,Q} <= {A,Q} >> 1; P<=P-1;
           state <= (P==1) ? DONE : TEST; end
    DONE:  state <= IDLE;
  endcase
end

Sequential multiplier core (add-and-shift loop).

Real-world applications

ALU multiplyDSP cores

The 5 Whys

1
Why FSM + datapath? Clean RTL realization.
2
Why {A,Q} concat shift? Aligns partial products.
3
Why counter status? Knows when n bits done.
4
Why non-blocking? Concurrent register updates.
5
Root cause: the ASMD multiplier maps directly to two HDL blocks.

Cheat sheet

Working principle

Controller FSM + {A,Q} datapath with one adder and a counter.
Synthesizable HDL for the add-and-shift multiplier.

Formulas & Boolean expressions

ADD state: if Q0, A <= A + B.
SHIFT state: {A,Q} <= {A,Q} >> 1; P <= P - 1.
Loop until P = 0, then DONE.
LOAD = A←0, load B,Q,P
ADD = if Q0: A←A+B
SHIFT = shr {A,Q}; P←P−1
DONE = product in {A,Q}

Key facts

State machine: IDLE, LOAD, ADD, SHIFT, DONE.
Non-blocking assignments for all registers.

Why it exists

Root cause: the ASMD multiplier maps directly to two HDL blocks.