Volume II: Digital Logic › Register Transfer Level Design

HDL Description of Design Example

Coding an ASMD design as two HDL blocks: controller FSM + datapath.

On this page:Description At a glance Theory HDL Applications 5 Whys Cheat sheet

Description

An ASMD chart codes cleanly into HDL as a controller (a state-machine always block) and a datapath (clocked register transfers gated by control signals). The controller asserts control outputs per state; the datapath performs the transfers and returns status to the controller.

Controller: state register + next-state/output combinational logic.
Datapath: registers updated by control-gated transfers.
Control outputs (load, inc, shift) enable datapath transfers.
Datapath status (zero, sign) feeds controller decisions.
Reset initializes both state and registers.
Non-blocking (<=) for all clocked state.
Separate combinational next-state logic.
One control signal per enabled transfer.
Enum/parameter state names.
Mirror the ASMD chart structure exactly.

At a glance

What

The HDL realization of an ASMD chart (controller + datapath).

Why

It turns the design chart into synthesizable hardware.

How

One FSM block for control, one set of clocked transfers for the datapath.

Where

Implementation of any RTL design example.

When

After the ASMD chart is finalized.

Think of it like…

Like splitting a play into a director (controller) calling cues and the actors (datapath) performing them — two coordinated scripts.

Two blocks

Controller: state register + next-state/output combinational logic.
Datapath: registers updated by control-gated transfers.
Control outputs (load, inc, shift) enable datapath transfers.
Datapath status (zero, sign) feeds controller decisions.
Reset initializes both state and registers.

Coding discipline

Non-blocking (<=) for all clocked state.
Separate combinational next-state logic.
One control signal per enabled transfer.
Enum/parameter state names.
Mirror the ASMD chart structure exactly.

Chart → code

ASMD element	HDL
state box	FSM state
transfer	datapath q<=...
control output	reg signal
decision	if(status)

HDL — Verilog · VHDL · SystemVerilog

// Controller
always @(posedge clk)
  if (rst) state <= IDLE; else state <= next;
always @(*) begin
  load=0; dec=0; next=state;
  case (state)
    IDLE: if (start) begin load=1; next=RUN; end
    RUN:  if (zero) next=IDLE; else dec=1;
  endcase
end
// Datapath
always @(posedge clk)
  if (load) R <= N; else if (dec) R <= R - 1;
assign zero = (R==0);

Controller + datapath skeleton (count-down example).

Real-world applications

Sequential designsTeaching RTL methodology

The 5 Whys

1
Why two blocks? Clean control/datapath separation.
2
Why control-gated transfers? FSM decides timing.
3
Why status feedback? Datapath conditions drive control.
4
Why mirror the chart? Correctness by construction.
5
Root cause: ASMD's two halves map to two HDL blocks.

Cheat sheet

Working principle

One FSM block for control, one set of clocked transfers for the datapath.
The HDL realization of an ASMD chart (controller + datapath).

Formulas & Boolean expressions

Non-blocking (<=) for all clocked state.
state box = FSM state
transfer = datapath q<=...
control output = reg signal
decision = if(status)

Key facts

Controller: state register + next-state/output combinational logic.
Non-blocking (<=) for all clocked state.

Why it exists

Root cause: ASMD's two halves map to two HDL blocks.