Latch-Up in CMOS

• It originates from the body-bias connection.
• Noise current together with the body-bias connection resistance creates a positive feedback loop that ultimately short-circuits power to ground.
• The parasitic BJT is formed by the CMOS device structure and needs a trigger voltage to fire.
• That trigger voltage comes from the body-bias resistance and the noise current.
• The trigger voltage is fixed because the device is fixed by the CMOS structure.
• The maximum noise current is also fixed for a given technology.
• Therefore the body-bias resistance must be controlled to avoid latch-up.
• This limit is what determines the maximum allowed spacing between tap cells.

KEY Latch-up is a parasitic BJT feedback loop; controlling body-bias resistance via tap-cell spacing prevents it.

14nm vs 7nm

Moving from a higher to a lower technology node brings more complex challenges, including:

• More crosstalk.
• More DRCs.
• More IR drop.
• Smaller area, leading to more congestion issues.
• Signal electromigration violations.
• Higher power dissipation.

KEY Going to 7nm worsens crosstalk, DRCs, IR drop, congestion, signal EM and power dissipation.