Analysis of Clocked Sequential Circuits
Given a sequential circuit, derive its state table, state diagram, and behavior.
Description
The reverse-engineering of a clocked circuit into equations, a state table, and a diagram. You must predict exactly how an existing circuit behaves over time. Write flip-flop input equations → next-state equations → state table → state diagram.
- Write each flip-flop's input equations from the logic.
- Substitute into the characteristic equation → next-state equations.
- Build the state table (present state + input → next state + output).
- Draw the state diagram from the table.
- Moore outputs depend on state only — labels sit on the state nodes.
- Mealy outputs depend on state and input — labels sit on the transitions.
- What: The reverse-engineering of a clocked circuit into equations, a state table, and a diagram.
- Why: You must predict exactly how an existing circuit behaves over time.
- How: Write flip-flop input equations → next-state equations → state table → state diagram.
- Where: Verifying designs, reading legacy schematics, exam analysis problems.
At a glance
What
The reverse-engineering of a clocked circuit into equations, a state table, and a diagram.
Why
You must predict exactly how an existing circuit behaves over time.
How
Write flip-flop input equations → next-state equations → state table → state diagram.
Where
Verifying designs, reading legacy schematics, exam analysis problems.
When
Any time you need the behavior of a given sequential circuit.
Think of it like…
Analysis is like reading sheet music to predict the tune: the equations are the notes, the state diagram is the melody you can now hum before playing.
Analysis steps
- Write each flip-flop's input equations from the logic.
- Substitute into the characteristic equation → next-state equations.
- Build the state table (present state + input → next state + output).
- Draw the state diagram from the table.
Mealy vs Moore in analysis
- Moore outputs depend on state only — labels sit on the state nodes.
- Mealy outputs depend on state and input — labels sit on the transitions.
State table shape
| Present state | Input | Next state | Output |
|---|---|---|---|
| S0 | 0 | S0 | 0 |
| S0 | 1 | S1 | 0 |
| S1 | 0 | S0 | 0 |
| S1 | 1 | S1 | 1 |
The 5 Whys
- 1
Why analyze? To know exactly how a built circuit behaves.
- 2
Why next-state equations? They capture where the machine goes each clock.
- 3
Why a state table? It enumerates every present-state/input case.
- 4
Why a state diagram? A picture makes the behavior graspable.
- 5
Root cause: equations → table → diagram is the bridge from gates to behavior.
Cheat sheet
Working principle
- Write flip-flop input equations → next-state equations → state table → state diagram.
- The reverse-engineering of a clocked circuit into equations, a state table, and a diagram.
Key facts
- Write each flip-flop's input equations from the logic.
- Moore outputs depend on state only — labels sit on the state nodes.
Why it exists
- Root cause: equations → table → diagram is the bridge from gates to behavior.