deassertion must meet the minimum required pulse width.

KEY Assertion applies reset, deassertion releases it - async deassertion can cause metastability.

Reset Recovery Time

Reset recovery time is a timing rule between the clock and reset signals, similar to setup time. It is the minimum time required between the deassertion of reset and the next active clock edge.

After reset is released it takes some time to stabilise; if the clock edge arrives immediately, the flip-flop can enter an unknown state and violate timing. The recovery check ensures there is enough time for the next clock edge to be effective.

KEY Reset recovery time is the minimum gap between reset deassertion and the next clock edge.

Reset Removal Time

Reset removal time is a timing rule between the clock and reset signals, similar to hold time. It is the minimum time required between the clock edge and the deassertion of reset.

The deasserted reset must not be captured on the clock edge at which it is launched; after the clock edge the reset signal must stay stable for at least the removal time.

KEY Reset removal time is the minimum gap between the clock edge and reset deassertion.

Ways to Fix a Timing Path

Yes, timing paths can be fixed. Methods include:

• Logic optimization.
• Using macros, and better placement of the logic/launch/capture flip-flops.
• Adding pipeline stages.
• Replicating drivers and splitting the receiving gates.
• Breaking a large serial operation into several smaller parallel operations.