Introduction
Memory stores many words of data; programmable logic devices store a circuit's function.
Description
This chapter covers two ways to use arrays of cells: memory, which stores data words you read and write, and programmable logic (ROM, PLA, PAL, CPLD, FPGA), which stores the configuration of a logic function. Both are built from a decoder feeding an array, differing only in whether the array holds data or logic.
- Memory stores binary information you can read back (and usually write).
- Programmable logic stores the truth table / product terms of a function.
- Both share the same skeleton: address decoder + cell array.
- Capacity is words × bits-per-word (e.g. 1K × 8).
- Volatile (RAM) loses data on power-off; non-volatile (ROM/flash) keeps it.
- Identical repeated cells pack far denser than random gates.
- One decoder amortizes addressing across the whole array.
- Programmability lets one chip serve many designs (lower cost, faster updates).
- Scaling memory is adding rows, not redesigning logic.
- The array structure makes test and yield-repair tractable.
At a glance
What
Large regular arrays of cells used either to store data (memory) or to store logic (programmable devices).
Why
Random logic doesn't scale; regular arrays are dense, cheap, and reconfigurable.
How
An address decoder selects a row of an array; the array supplies data bits or product terms.
Where
Main memory, caches, ROMs, FPGAs — the bulk of every chip's transistors.
When
Whenever you need bulk storage or field-reconfigurable logic.
Think of it like…
Think of a giant chest of numbered drawers: a memory chest holds papers you swap in/out; a programmable-logic chest holds wiring instructions that define a machine.
Two array uses
- Memory stores binary information you can read back (and usually write).
- Programmable logic stores the truth table / product terms of a function.
- Both share the same skeleton: address decoder + cell array.
- Capacity is words × bits-per-word (e.g. 1K × 8).
- Volatile (RAM) loses data on power-off; non-volatile (ROM/flash) keeps it.
Why regular arrays
- Identical repeated cells pack far denser than random gates.
- One decoder amortizes addressing across the whole array.
- Programmability lets one chip serve many designs (lower cost, faster updates).
- Scaling memory is adding rows, not redesigning logic.
- The array structure makes test and yield-repair tractable.
Device families
| Device | Array stores | Writable? |
|---|---|---|
| RAM | data | yes (volatile) |
| ROM | logic/data | once / factory |
| PLA / PAL | logic terms | once / few |
| CPLD / FPGA | logic config | many (reprogram) |
Real-world applications
The 5 Whys
- 1
Why arrays? Regular cells scale where random logic can't.
- 2
Why a decoder? To pick one row from thousands with few wires.
- 3
Why programmable logic? One chip, many functions, fast turnaround.
- 4
Why volatile vs non-volatile? Speed/cost vs retention trade-off.
- 5
Root cause: a decoder + dense cell array is the universal pattern for bulk storage and logic.
Cheat sheet
Working principle
- An address decoder selects a row of an array; the array supplies data bits or product terms.
- Large regular arrays of cells used either to store data (memory) or to store logic (programmable devices).
Key facts
- Memory stores binary information you can read back (and usually write).
- Identical repeated cells pack far denser than random gates.
Why it exists
- Root cause: a decoder + dense cell array is the universal pattern for bulk storage and logic.