Storage Elements: Flip-Flops
Flip-flops store one bit and change only on a clock edge — the workhorse of synchronous design.
Description
An edge-triggered one-bit memory: it samples its input only at the clock edge. Edge-triggering removes the transparency hazard of latches, enabling reliable clocking. A master-slave or edge-detect structure captures D/J-K/T exactly at the rising (or falling) edge.
- D: Q⁺ = D — captures the data input each edge (most common).
- JK: 00 hold, 01 reset, 10 set, 11 toggle — the universal flip-flop.
- T: toggles when T=1, holds when T=0 — ideal for counters.
- SR: set/reset with a forbidden 11 input (rarely used directly).
- Latch = level-sensitive (transparent while enabled).
- Flip-flop = edge-triggered (samples only at the clock transition).
- Setup/hold times bound how close to the edge the input may change.
- What: An edge-triggered one-bit memory: it samples its input only at the clock edge.
- Why: Edge-triggering removes the transparency hazard of latches, enabling reliable clocking.
- How: A master-slave or edge-detect structure captures D/J-K/T exactly at the rising (or falling) edge.
At a glance
What
An edge-triggered one-bit memory: it samples its input only at the clock edge.
Why
Edge-triggering removes the transparency hazard of latches, enabling reliable clocking.
How
A master-slave or edge-detect structure captures D/J-K/T exactly at the rising (or falling) edge.
Where
Registers, counters, pipelines, FSM state — essentially all synchronous logic.
When
Whenever state must update once per clock, predictably.
Think of it like…
A flip-flop is a camera shutter: it ignores the scene continuously and only captures the picture (input) at the precise instant the clock 'clicks'.
The four types
- D: Q⁺ = D — captures the data input each edge (most common).
- JK: 00 hold, 01 reset, 10 set, 11 toggle — the universal flip-flop.
- T: toggles when T=1, holds when T=0 — ideal for counters.
- SR: set/reset with a forbidden 11 input (rarely used directly).
Edge vs level
- Latch = level-sensitive (transparent while enabled).
- Flip-flop = edge-triggered (samples only at the clock transition).
- Setup/hold times bound how close to the edge the input may change.
Characteristic equations
| Flip-flop | Q⁺ |
|---|---|
| D | D |
| JK | J·Q′ + K′·Q |
| T | T ⊕ Q |
| SR | S + R′·Q (SR = 0) |
JK excitation (design direction)
| Q | Q⁺ | J | K |
|---|---|---|---|
| 0 | 0 | 0 | X |
| 0 | 1 | 1 | X |
| 1 | 0 | X | 1 |
| 1 | 1 | X | 0 |
Black-box view
Inputs on the left → outputs on the right · particles show signal direction
flip-flop · live waveform
▶ live simulatorSet inputs, then Run for a live clock (or Step one edge) and watch Q on the waveform.
| D | Q⁺ | note |
|---|---|---|
| 0 | 0 | reset |
| 1 | 1 | set |
Characteristic equation: Q⁺ = D
HDL — Verilog · VHDL · SystemVerilog
module dff(input clk, rst_n, d, output reg q);
always @(posedge clk or negedge rst_n)
if (!rst_n) q <= 1'b0;
else q <= d;
endmoduleEdge-triggered D flip-flop with asynchronous reset — the canonical synchronous cell.
Real-world applications
The 5 Whys
- 1
Why flip-flops over latches? Edge-triggering kills transparency hazards.
- 2
Why does that matter? Feedback loops would race if storage were transparent.
- 3
Why one capture per edge? Makes every register update at a single, known instant.
- 4
Why setup/hold times? The input must be stable around the edge to capture cleanly.
- 5
Root cause: sampling at an instant (not a level) is what makes synchronous design reliable.
Cheat sheet
Working principle
- A master-slave or edge-detect structure captures D/J-K/T exactly at the rising (or falling) edge.
- An edge-triggered one-bit memory: it samples its input only at the clock edge.
Formulas & Boolean expressions
- D flip-flop: Q⁺ = D
- JK flip-flop: Q⁺ = J·Q′ + K′·Q
- T flip-flop: Q⁺ = T ⊕ Q
- SR flip-flop: Q⁺ = S + R′·Q (with S·R = 0)
- D: Q⁺ = D — captures the data input each edge (most common).
- T: toggles when T=1, holds when T=0 — ideal for counters.
- Latch = level-sensitive (transparent while enabled).
- Flip-flop = edge-triggered (samples only at the clock transition).
Key facts
- D: Q⁺ = D — captures the data input each edge (most common).
- Latch = level-sensitive (transparent while enabled).
Why it exists
- Root cause: sampling at an instant (not a level) is what makes synchronous design reliable.