Volume II: Digital Logic › Register Transfer Level Design

RTL Descriptions

Writing register transfers as synthesizable HDL.

On this page:Description At a glance Theory HDL Applications 5 Whys Cheat sheet

Description

An RTL description in HDL captures register transfers in clocked always/process blocks. Each register is updated with a non-blocking assignment under its control condition; the combinational next-value logic sits in separate statements. This is the everyday form of synthesizable design.

always @(posedge clk): each register transfer as q <= expr.
Guard transfers with if (control_condition).
Use non-blocking (<=) so transfers appear concurrent.
Reset defines initial register values.
Functional units (+, shifts) appear in the RHS expressions.
Datapath registers updated in clocked blocks.
Control signals come from the controller FSM.
Each control signal enables a specific transfer.
Keep combinational next-state separate from state register.
This mirrors the RTL notation directly.

At a glance

What

HDL that expresses register transfers for synthesis.

Why

It is the actual code that becomes datapath hardware.

How

Clocked block + non-blocking assignments guarded by control conditions.

Where

All RTL design.

When

When turning RTL notation into real hardware.

Think of it like…

An RTL description is the script handed to the actors (flip-flops): each line says exactly what to do on the next cue.

Coding register transfers

always @(posedge clk): each register transfer as q <= expr.
Guard transfers with if (control_condition).
Use non-blocking (<=) so transfers appear concurrent.
Reset defines initial register values.
Functional units (+, shifts) appear in the RHS expressions.

Datapath + control split

Datapath registers updated in clocked blocks.
Control signals come from the controller FSM.
Each control signal enables a specific transfer.
Keep combinational next-state separate from state register.
This mirrors the RTL notation directly.

Notation → HDL

RTL	Verilog
R ← R1	R <= R1;
if(P): R ← R+1	if (P) R <= R + 1;
R ← shr R	R <= R >> 1;

HDL — Verilog · VHDL · SystemVerilog

always @(posedge clk) begin
  if (rst)      R <= 0;
  else if (ld)  R <= data_in;   // R <- data_in
  else if (inc) R <= R + 1'b1;  // R <- R + 1
  else if (sh)  R <= R >> 1;    // R <- shr R
end

Real-world applications

Datapath RTLCPU register file logic

The 5 Whys

1
Why HDL RTL? It synthesizes to real datapath.
2
Why non-blocking? Models concurrent register updates.
3
Why guard transfers? Control decides when they fire.
4
Why split control? Clean, race-free, scalable design.
5
Root cause: clocked non-blocking assignments are flip-flop transfers in code.

Cheat sheet

Working principle

Clocked block + non-blocking assignments guarded by control conditions.
HDL that expresses register transfers for synthesis.

Formulas & Boolean expressions

always @(posedge clk): each register transfer as q <= expr.
Use non-blocking (<=) so transfers appear concurrent.
R ← R1 = R <= R1;
if(P): R ← R+1 = if (P) R <= R + 1;
R ← shr R = R <= R >> 1;

Key facts

always @(posedge clk): each register transfer as q <= expr.
Datapath registers updated in clocked blocks.

Why it exists

Root cause: clocked non-blocking assignments are flip-flop transfers in code.