Design Procedure
The recipe to build a synchronous sequential circuit from a word specification.
Description
A step-by-step flow from specification to a clocked sequential circuit. A disciplined flow yields correct, minimal FSMs without missed transitions. Spec → state diagram → state table → encode → excitation → flip-flop logic → draw.
- Derive a state diagram from the word problem.
- Build the state table; reduce and assign codes.
- Pick a flip-flop type and use its excitation table.
- Get flip-flop input equations (K-map each).
- Draw the circuit and verify.
- D simplifies the procedure (input equation = next-state equation).
- JK/T can reduce logic via don't-cares in the excitation table.
- What: A step-by-step flow from specification to a clocked sequential circuit.
- Why: A disciplined flow yields correct, minimal FSMs without missed transitions.
- How: Spec → state diagram → state table → encode → excitation → flip-flop logic → draw.
At a glance
What
A step-by-step flow from specification to a clocked sequential circuit.
Why
A disciplined flow yields correct, minimal FSMs without missed transitions.
How
Spec → state diagram → state table → encode → excitation → flip-flop logic → draw.
Where
Designing counters, sequence detectors, and controllers.
When
At the start of any sequential design.
Think of it like…
Designing an FSM is like choreographing a dance: first sketch the moves (state diagram), number them (encode), then write exact step-by-step instructions (flip-flop equations).
The steps
- Derive a state diagram from the word problem.
- Build the state table; reduce and assign codes.
- Pick a flip-flop type and use its excitation table.
- Get flip-flop input equations (K-map each).
- Draw the circuit and verify.
Choosing the flip-flop
- D simplifies the procedure (input equation = next-state equation).
- JK/T can reduce logic via don't-cares in the excitation table.
Excitation tables (recap)
| Q→Q⁺ | D | JK | T |
|---|---|---|---|
| 0→0 | 0 | 0 X | 0 |
| 0→1 | 1 | 1 X | 1 |
| 1→0 | 0 | X 1 | 1 |
| 1→1 | 1 | X 0 | 0 |
Experiment with each flip-flop type
▶ live simulatorSet inputs, then Run for a live clock (or Step one edge) and watch Q on the waveform.
| J | K | Q⁺ | note |
|---|---|---|---|
| 0 | 0 | Q | no change |
| 0 | 1 | 0 | reset |
| 1 | 0 | 1 | set |
| 1 | 1 | Q′ | toggle |
Characteristic equation: Q⁺ = JQ′ + K′Q
The 5 Whys
- 1
Why a procedure? To avoid missed states or transitions.
- 2
Why a state diagram first? It captures the intended behavior unambiguously.
- 3
Why excitation tables? They tell which inputs drive each required transition.
- 4
Why K-map the inputs? To minimize the next-state logic.
- 5
Root cause: a structured flow makes correct, minimal FSM hardware repeatable.
Cheat sheet
Working principle
- Spec → state diagram → state table → encode → excitation → flip-flop logic → draw.
- A step-by-step flow from specification to a clocked sequential circuit.
Formulas & Boolean expressions
- D simplifies the procedure (input equation = next-state equation).
Key facts
- Derive a state diagram from the word problem.
- D simplifies the procedure (input equation = next-state equation).
Why it exists
- Root cause: a structured flow makes correct, minimal FSM hardware repeatable.