Volume II: Digital Logic › Gate-Level Minimization

Truth Tables in HDLs

Describing logic directly by its truth table in HDL — Verilog user-defined primitives.

On this page:Description At a glance Theory HDL Applications 5 Whys Cheat sheet

Description

Some logic is clearest as a raw truth table. Verilog supports User-Defined Primitives (UDPs) declared with primitive…endprimitive and a table…endtable block, listing inputs then the single output per row. It is a tabular alternative to equation- or gate-based modeling.

Declared with primitive … endprimitive (not module).
Exactly one output, listed first and declared output.
Any number of inputs, in declared order.
Table enclosed by table … endtable.
Each row: input values, a colon, then the output, then a semicolon.
A UDP can be instantiated like a built-in gate.
Combinational UDPs map a row of inputs to one output.
Sequential UDPs add current state and an edge column.
Good for small, well-defined primitives.
Not all HDLs support truth-table description.

At a glance

What

Specifying a combinational (or sequential) function by an explicit table in HDL.

Why

When a function is most natural as a table, a UDP captures it directly.

How

Verilog primitive with one output first, inputs after, and a table of rows.

Where

Library primitive modeling and concise combinational specs.

When

When a truth table is clearer than equations or gates.

Think of it like…

A UDP is handing the tool a finished answer key (the table) instead of describing how to compute each answer.

Verilog UDP rules

Declared with primitive … endprimitive (not module).
Exactly one output, listed first and declared output.
Any number of inputs, in declared order.
Table enclosed by table … endtable.
Each row: input values, a colon, then the output, then a semicolon.

Use

A UDP can be instantiated like a built-in gate.
Combinational UDPs map a row of inputs to one output.
Sequential UDPs add current state and an edge column.
Good for small, well-defined primitives.
Not all HDLs support truth-table description.

UDP row format

Field	Meaning
inputs	in declared order
:	separator
output	single value
;	row terminator

Truth-table behavior on gates

▶ live simulator

Click a terminal (A/B) to toggle it · glowing wires carry a logic 1 · the lamp is output Y

A	B	Y
0	0	0
0	1	0
1	0	0
1	1	1

HDL — Verilog · VHDL · SystemVerilog

primitive udp_maj (Y, A, B, C);
  output Y; input A, B, C;
  table
  // A B C : Y
     0 0 0 : 0;
     0 0 1 : 0;
     0 1 0 : 0;
     0 1 1 : 1;
     1 0 0 : 0;
     1 0 1 : 1;
     1 1 0 : 1;
     1 1 1 : 1;
  endtable
endprimitive

Verilog user-defined primitive (UDP) describing a function by truth table.

Real-world applications

Library primitivesConcise combinational specs

The 5 Whys

1
Why table-based HDL? Some functions are clearest as tables.
2
Why one output? UDP definition restricts to a single output.
3
Why ordered inputs? The table columns bind by position.
4
Why UDPs? Concise reusable primitives.
5
Root cause: a table is sometimes the most direct, least error-prone spec.

Cheat sheet

Working principle

Verilog primitive with one output first, inputs after, and a table of rows.
Specifying a combinational (or sequential) function by an explicit table in HDL.

Formulas & Boolean expressions

inputs = in declared order
: = separator
output = single value
; = row terminator

Key facts

Declared with primitive … endprimitive (not module).
A UDP can be instantiated like a built-in gate.

Why it exists

Root cause: a table is sometimes the most direct, least error-prone spec.