• The IR-drop margin depends on the IR drop you plan to achieve - if you meet a 3% IR drop, you have the flexibility to reduce the flat margin in the OCV derate value.
• If endcap cells are not used, you must add more margin to the derating factors, because every standard cell is characterized assuming it sits in the middle of the chip where stress is lower; a cell at the chip edge sees more stress and may underperform. Many such factors guide the foundry and company in raising or lowering the flat margin.

KEY OCV covers only PVT, but jitter comes from PLL noise, so clock uncertainties are kept as a separate margin post-CTS.

Fixing Core Congestion Pre-CTS

• Change the maximum density target and re-run placement to see whether congestion comes under control.
• If cell and pin density are high, apply cell padding, module padding or partial density screens to those cells.
• Check for a floorplan problem that is causing a module to be split apart.
• Check whether a buffer or inverter chain is running through that area because of a floorplan issue.

KEY Adjust density targets, pad dense cells, and look for floorplan issues splitting modules or routing chains through the area.

Inverter on the Capture Clock Pin

Before the inverter is added, a full clock cycle is available for the setup check.

After the inverter is added, the path becomes a half-cycle path for setup, so setup timing becomes very tight. Hold, however, is not a concern: the capture clock now arrives half a period earlier (on the negative edge) while the launch clock comes later (on the positive edge), so the hold path gains an extra half cycle and becomes less critical.