are all commonly available.

• It uses lookup-table-based or constant I/V device models and the Elmore wire-delay model.
• It performs worst-case analysis across all possible paths to check delay requirements, including potential false paths.
• It is efficient only for fully synchronous designs.

In summary, STA breaks the design into timing paths, calculates the signal propagation delay along each path, and checks for timing-constraint violations inside the design and at the I/O interface.

KEY STA needs no I/O variables, uses common inputs and worst-case analysis, but suits only fully synchronous designs.

Major Functions of STA

STA checks the following:

• Setup time.
• Hold time.
• Reset removal and reset recovery time.
• Clock gating.
• Minimum and maximum fan-out range.
• Maximum capacitance range.
• Clock pulse-width requirements.

KEY STA checks setup, hold, recovery/removal, clock gating, fan-out, max cap and clock pulse width.

Input Files Required to Run STA

• Gate-level netlist.
• Parasitic files.
• Constraints.
• General setup scripts.

KEY STA needs the gate-level netlist, parasitics, constraints and setup scripts.