Logo
VLSI Physical Design  ›  Ch 7. Setup, Hold & Timing

Major STA Tools

  • Cadence Encounter.
  • Synopsys PrimeTime.
  • Altera Quartus II.
  • IBM EinsTimer.

KEY Common STA tools: Cadence Encounter, Synopsys PrimeTime, Altera Quartus II, IBM EinsTimer.

What STA Checks

STA mainly performs setup and hold checks, but it also verifies that the assumptions made during timing analysis hold - for example that cells stay within their library characterization range for input slope and output load, and that the clock waveform matches expectations. A partial list of what it checks:

  • Setup timing and hold timing.
  • Removal and recovery timing on resets.
  • Clock-gating checks.
  • Min/max transition times.
  • Min/max fanout and max capacitance.
  • Min/max timing between two points on a timing-path segment.
  • Latch time borrowing and clock pulse-width requirements.

KEY STA checks setup/hold, removal/recovery, clock gating, DRVs, time borrowing and pulse widths.

Signing Off With a Hold Violation

No - a design with hold violations cannot be signed off, because hold violations are functional failures.

Setup violations are frequency dependent and can be avoided by lowering the clock frequency. Hold violations from the same clock-edge race are frequency independent, so they cannot be tuned away; they can capture unintended data and push the state machine into an unknown state.