KEY Tap gated branches into the shared main tree to cut buffers, insertion delay and OCV impact, versus separate trees.

Clock Tree Build Options

Five special clock options greatly expand control over clock building:

Clock phase:

• A clock phase is a timer event tied to a particular edge of the source clock.
• Each clock domain is created with two clock phases - the rising edge and the falling edge - named after the timing clock with an R or F suffix.
• These phases propagate through the circuit to the endpoints so that events at clock pins can be traced back to the defined clocks.
• Since the tool can propagate multiple clocks, a single clock pin can have two or more phases. For example, if CLKA and CLKB feed the i0 and i1 inputs of a 2:1 MUX, every clock pin in the MUX fan-out has four phases: CLKA.R, CLKA.F, CLKB.R and CLKB.F.

Skew phase:

• A skew phase is a collection of clock phases; each clock phase goes into the skew phase of the same name.
• When a clock is defined, skew phases are created automatically with the same names as the clock phases.

Skew group:

• Clock-tree skew balancing is done per skew group. A skew group is