Skew Focus vs Timing Closure at CTS

Reducing clock skew is not only a performance issue, it is also a manufacturing issue.

• Scan-based testing, the most common way to structurally test chips for manufacturing defects, needs minimum skew to shift scan vectors error-free and detect stuck-at and delay faults.
• Hold failures at the best-case PVT corner are common in scan chains because there is usually no combinational logic between one flop's output and the scan input of the next flop.
• Managing and minimising clock skew often resolves those scan hold failures.

KEY Low skew is also a manufacturing requirement - scan-based testing needs minimum skew to shift vectors and avoid hold failures.

Fixing Skew Across Three Flops

Use useful skew - borrow time across the B flop. Pull the clock at B's clock pin earlier by 50ps; this tightens the A-to-B path (which has plenty of margin) while relaxing the failing B-to-C path.

KEY Apply useful skew - advance B's clock by 50ps to borrow margin from the A-to-B path into the failing B-to-C path.

Clock Uncertainty and Signal Integrity

No. Clock uncertainty settings have no effect on the calculation of crosstalk arrival windows.

KEY No - clock uncertainty does not change crosstalk arrival-window calculation.

Why Route After CTS, Not Before

• Routing is generally timing-driven, and meaningful timing-driven routing is only possible once the clock tree has been built.
• If the design is routed first, the clock tree will not get proper routing resources afterwards, so clock nets detour, which degrades insertion delay and skew.