Setup vs Hold Violation - Which Is Worse

A setup violation is frequency-dependent - it can be reduced or removed by lowering the clock frequency. A hold violation is a true functional failure, independent of frequency, and slowing the clock will not fix it (it causes a data race).

So a design with a setup violation can still be used at a slower clock, but a hold violation makes the design unusable.

KEY Hold violations are worse - they are functional failures that frequency changes cannot fix.

Time Stealing

Time stealing means deliberately adjusting the clock phase at the capturing flip-flop so that the data arrival time still meets the timing constraints. It is used when a particular logic partition needs extra, deterministic time decided up front.

KEY Time stealing shifts the capture flop's clock phase to give a slow block more time.

Time Borrowing vs Time Stealing

• Time borrowing applies to latch-based designs; time stealing applies to flip-flop-based designs.
• Borrowing takes spare time from shorter next-stage paths and gives it to a longer path; stealing adjusts the capture flop's clock cycle to match the data arrival time.
• Borrowing does not touch the clock phase (the latch handles it automatically through the pipeline); stealing shifts the clock phase, so the designer must ensure the next stage's delay stays below the period minus the phase shift.

KEY Borrowing = automatic, latch-based, no phase change; stealing = manual flop-clock phase adjustment.