KEY AOCV reflects cell doping/process; wire etch variation is already in extraction, so wires use flat derates.

What-If Analysis in STA

• What-if analysis means manually targeting specific cells for a timing fix and then measuring the impact that change has on the design.
• It can be applied to any design target, not just timing.

KEY What-if analysis manually targets cells for a fix and measures the resulting impact on the design.

-nworst 1 vs -max_paths 1

• '-max_paths 1' reports only the single worst (WNS) path for the respective path group.
• '-nworst 1' reports the worst path per endpoint within each defined group.

KEY -max_paths 1 gives the single WNS path per group; -nworst 1 gives the worst path per endpoint.

Categorising Timing into Path Groups

• REG2REG - register-to-register paths, the preferred focus at block level.
• IN2REG - input-port to register paths.
• REG2OUT - register to output-port paths.
• IN2OUT - input-port to output-port paths.
• User-defined timing groups can also be created.
• By default the tool creates path groups based on the clock's defined in the design.

KEY Timing groups are REG2REG, IN2REG, REG2OUT, IN2OUT, plus user-defined and tool-default per-clock groups.

Fixing Multi-Cycle Path Violations

• A multi-cycle path is determined by the data-path delay - it applies when that delay is much larger than the clock period.
• The data path follows the coded architecture.