Logic Simulation
Running the HDL model over time to observe waveforms and verify behavior.
Description
Logic simulation executes an HDL model with testbench stimulus, computing signal values over simulated time and producing waveforms. It validates functionality (and, with delays, timing) before committing to hardware — the core feedback loop of digital design.
- Event-driven: re-evaluate logic only when a signal changes.
- Maintains a time wheel of scheduled events.
- Functional sim ignores delays; timing sim includes them.
- Outputs waveforms (VCD) for inspection.
- Driven by the testbench stimulus.
- Functional bugs (wrong outputs).
- Uninitialized / X-propagation issues.
- Race conditions in poorly written RTL.
- With delays: setup/hold and glitch timing.
- Coverage gaps (untested cases).
At a glance
What
Time-stepped execution of an HDL model to observe its signals.
Why
It verifies logic (and timing) cheaply, before fabrication.
How
An event-driven simulator evaluates signals as inputs change.
Where
Every step of RTL verification.
When
Continuously while developing and after each change.
Think of it like…
Logic simulation is a flight simulator for circuits: fly the design through scenarios and watch the instruments (waveforms) before risking a real aircraft (silicon).
How simulation works
- Event-driven: re-evaluate logic only when a signal changes.
- Maintains a time wheel of scheduled events.
- Functional sim ignores delays; timing sim includes them.
- Outputs waveforms (VCD) for inspection.
- Driven by the testbench stimulus.
What it catches
- Functional bugs (wrong outputs).
- Uninitialized / X-propagation issues.
- Race conditions in poorly written RTL.
- With delays: setup/hold and glitch timing.
- Coverage gaps (untested cases).
Simulation types
| Type | Includes delay? |
|---|---|
| Functional/RTL | no |
| Gate-level | yes (cell delays) |
| Timing (SDF) | yes (annotated) |
Real-world applications
The 5 Whys
- 1
Why simulate? Catch bugs before costly fabrication.
- 2
Why event-driven? Only changed signals need re-evaluation (fast).
- 3
Why waveforms? Visual debugging of behavior over time.
- 4
Why timing sim? To verify real-delay correctness.
- 5
Root cause: simulation is the cheap, fast feedback loop of hardware design.
Cheat sheet
Working principle
- An event-driven simulator evaluates signals as inputs change.
- Time-stepped execution of an HDL model to observe its signals.
Formulas & Boolean expressions
- Functional/RTL = no
- Gate-level = yes (cell delays)
- Timing (SDF) = yes (annotated)
Key facts
- Event-driven: re-evaluate logic only when a signal changes.
- Functional bugs (wrong outputs).
Why it exists
- Root cause: simulation is the cheap, fast feedback loop of hardware design.