Volume II: Digital Logic › Combinational Logic

Behavioral Modeling

Describing what logic does (algorithmically) rather than its gates.

On this page:Description At a glance Theory HDL Applications 5 Whys Cheat sheet

Description

Behavioral modeling specifies a circuit by its behavior using procedural statements (always blocks, if/case) rather than gate interconnections. For combinational logic use always @(*) with blocking assignments and assign every output on every path to avoid inferred latches.

Use always @(*) so all inputs are in the sensitivity list.
Use blocking assignments (=) for combinational logic.
Assign every output on every branch (else/default).
Incomplete assignment infers an unwanted latch.
case/if map naturally to muxes/priority logic.
Concise: describe intent, not wiring.
Synthesizer optimizes gates for you.
Easier to read and maintain.
Portable across technologies.
Pairs with testbenches for verification.

At a glance

What

HDL modeling by algorithmic behavior, not explicit gates.

Why

It is faster to write and lets the synthesizer choose the gates.

How

Procedural blocks (always @(*)) with if/case and full assignment.

Where

Most real RTL is behavioral.

When

Whenever the behavior is easier to state than the gate netlist.

Think of it like…

Behavioral modeling is writing a recipe ('whisk until smooth') instead of specifying each muscle movement (gates).

Combinational behavioral rules

Use always @(*) so all inputs are in the sensitivity list.
Use blocking assignments (=) for combinational logic.
Assign every output on every branch (else/default).
Incomplete assignment infers an unwanted latch.
case/if map naturally to muxes/priority logic.

Why behavioral

Concise: describe intent, not wiring.
Synthesizer optimizes gates for you.
Easier to read and maintain.
Portable across technologies.
Pairs with testbenches for verification.

Combinational checklist

Concern	Rule
Sensitivity	@(*)
Assignment	blocking =
Completeness	assign on all paths
No latch	else/default

The mux this behavioral code describes

▶ live simulator

Select = 00 (0) → routes D0 to Y. Click any D or S to toggle.

HDL — Verilog · VHDL · SystemVerilog

module mux4(input [3:0] d, input [1:0] s, output reg y);
  always @(*)
    case (s)
      2'b00: y = d[0]; 2'b01: y = d[1];
      2'b10: y = d[2]; 2'b11: y = d[3];
    endcase
endmodule

Behavioral combinational logic — a 4-to-1 mux via case.

Real-world applications

Most RTL designControl + datapath description

The 5 Whys

1
Why behavioral? Faster to write than gate netlists.
2
Why @(*)? Missing inputs cause sim/synth mismatch.
3
Why assign all paths? Avoid inferred latches.
4
Why blocking '='? Matches combinational semantics.
5
Root cause: stating behavior lets tools synthesize optimal gates.

Cheat sheet

Working principle

Procedural blocks (always @(*)) with if/case and full assignment.
HDL modeling by algorithmic behavior, not explicit gates.

Formulas & Boolean expressions

Use blocking assignments (=) for combinational logic.
Sensitivity = @(*)
Assignment = blocking =
Completeness = assign on all paths
No latch = else/default

Key facts

Use always @(*) so all inputs are in the sensitivity list.
Concise: describe intent, not wiring.

Why it exists

Root cause: stating behavior lets tools synthesize optimal gates.