Targets of CTS

• At SOC level, insertion delay is a hard requirement to meet (for example, a WiFi chip may have a maximum insertion delay of 5 ns).
• Balance the clock only across blocks that actually communicate with each other.
• Clock transition is a hard limit that must be met for the block, because it affects:
• Sequential cell delay.
• The setup and hold requirements of the flop.
• Short-circuit current - sharper transitions reduce it.
• Achieving a sharper transition needs bigger cells, which consume more switching power.
• Achieving a sharper transition also needs more levels in the tree.

KEY CTS targets: meet hard insertion-delay and clock-transition limits, and balance only communicating blocks.

Deciding a Block's Minimum Insertion Delay

• It is driven by how the block communicates with the other blocks.
• It must be decided and then applied in the design.

KEY A block's minimum insertion delay is set by its communication with other blocks and must be applied in design.

Undefined Macro Insertion Delay in CTS

• Memory-to-register paths will be affected for setup timing.
• Register-to-memory paths will be affected for hold timing.

KEY Undefined macro insertion delay breaks MEM2REG setup and REG2MEM hold timing.

Extra Spacing on Clock Nets

The extra spacing is given to prevent the clock from inducing crosstalk on the neighbouring data nets.

KEY Clock nets get extra spacing to avoid coupling crosstalk onto adjacent data nets.