KEY The four/five classic paths: reg-to-reg, input-to-reg, reg-to-output, input-to-output, plus macro paths.

Launch Edge and Capture Edge

In synchronous design, data generation, computation and transfer all happen within a clock cycle. The active clock edge at which the launching flip-flop drives data from its input to its output is the launch edge.

At the next active clock edge, the capturing flip-flop samples the data arriving at its input - that edge is the capture edge. The data must meet its timing requirements before this capture edge.

KEY Launch edge = data leaves the source flop; capture edge = the next flop samples it.

Setup Time and Hold Time

Setup time is how long input data must be stable before the capture clock edge. If data is not settled in time, the flip-flop can go metastable.

Hold time is how long data must remain stable after the capture clock edge.

KEY Setup = stable-before-edge requirement, hold = stable-after-edge requirement.