What Cell Delay Depends On

Cell delay depends on input slew, output load, the input signal vector sequence, multiple input switching (MIS), threshold voltage, carrier mobility, temperature, channel length, VDD, and gate oxide thickness.

KEY Cell delay depends on slew, load, input pattern/MIS, Vt, mobility, temperature, channel length, VDD and oxide thickness.

Poor Clock Transition - Setup and Hold

Several distinct cases must be considered:

• Case 1 - bad transition on the launch clock pin but good on the capture clock: the launch register's clk-to-Q delay increases, shrinking the setup window, so setup gets worse and hold gets better.
• Case 2 - bad transition on the capture clock but good on the launch clock: the capture path delay increases and the library setup margin worsens; the net effect on setup depends on the combined impact of the larger library margin plus the added capture-path delay.
• Case 3 - bad transition on clock inverters other than the CK pins of the launch and capture registers: several sub-cases apply.
• Case 3A - bad transition on the common clock path: it delays both launch and capture paths equally, so it affects neither setup nor hold.
• Case 3B - bad transition on the launch clock path only: the launch path is delayed, which is bad for setup but good for hold.
• Case 3C - bad transition on the capture clock path only: the capture path is delayed, which is good for setup but bad for hold.

KEY Effect of a poor clock transition on setup/hold depends on whether it sits on the launch, capture or common clock path.

Advanced Waveform Propagation (AWP)

At a receiver input the signal waveform becomes distorted because of the Miller effect and the long-tail effect. Ignoring these effects makes cell delays optimistic.

Enabling AWP through time.delay_calc_waveform_analysis_mode yields