KEY MV designs cut power by lowering voltage, gating activity and shutting down idle domains.

Isolation in an ON-OFF Design

• A signal going from an ON block to an OFF block causes no issue.
• A signal going from an OFF block to an ON block is a problem - its state is unknown, so it propagates an X into the system.
• An undefined input can leave a CMOS gate's input mid-rail, effectively shorting power to ground through that gate.
• This produces short-circuit current.
• Isolation cells (AND or OR type) clamp the signal to a known fixed value - 0 for an AND-type ISO cell, 1 for an OR-type.

KEY ISO cells clamp OFF-to-ON signals to a known value, preventing X propagation and short-circuit current.

Cells Used in Low-Power Techniques

• Isolation (ISO) cells.
• Level shifter (LS) cells.
• Power switch cells.

KEY Low-power designs use isolation cells, level shifters and power switches.

Voltage Area vs Power Domain

A power domain becomes a voltage area once it is assigned an actual physical region of the design - in other words, the VA is the physical realisation of a power domain.

KEY A voltage area is a power domain that has been given a physical region on the die.

Spotting Isolation From the Inputs

The UPF file will contain a create_isolation_rule command.

KEY A create_isolation_rule statement in the UPF indicates the design uses isolation.